What is the treatment of Ziguang Zhanrui (digital IC front-end small Shuo Shuo)?

There is usually a year-end bonus in May, usually for two months, but there are also three to five months. It's just a small proportion. Usually, the year-end bonus is based on the number of overtime hours.

Job responsibilities:

1. Design and implementation of testability of development and maintenance module and SoC chip.

2. Plan the test schemes of mbist, Caton at and Extreme Speed, and deeply understand the principles of each test scheme.

3. Cooperate with STA engineer to solve problems related to sdc and test mode timing.

4. Cooperate with ate test engineer to solve problems related to mass production test.

5. Complete ATPG verification independently.

Qualifications:

1, master degree or above in electronics, communication or computer related field.

2.2 years working experience in DFT; Familiar with ASIC design.

3. Skillfully use Synopsys or Mentor DFT tools.

4. Skillful use of Perl(Python), Tcl and Shell scripts is preferred.

5. Experience in ASIC process of 28 nm and below is preferred.

6. Experience in maintenance and mass production is preferred.