Verilog outputs a specified number of pulses after frequency division, and then pulls the signal high.

Using Verilog language to realize arbitrary integer frequency divider? Frequency divider is one of the most commonly used basic designs in FPGA design, although PLL resources integrated by chip manufacturers, such as DLL of Xil, are widely used for clock frequency division, multiplication and phase shift. However, for the basic design with low clock requirements, the frequency division and phase shift of the clock by language is still very popular. First of all, this method can save PLL resources inside the chip, and it can achieve the purpose of operating the clock by consuming few logic units. On the other hand, by dividing the clock by language design, we can see the designer's understanding of design language. Therefore, many employers often ask candidates to write a frequency divider (such as odd frequency divider) to assess the design level and understanding ability of candidates. Let's talk about the frequency division methods of various frequency division coefficients:

First, even multiple frequency division: even multiple frequency division should be familiar to everyone, and it is completely possible to count with a counter. If n times even frequency division is performed, the counter can be triggered by the clock to be divided. When the counter counts from 0 to N/2- 1, the output clock flips and gives the counter a reset signal so that the next clock can count from zero. In this cycle. This method can realize arbitrary even frequency division. Only one D flip-flop and one NOT gate are needed in the circuit, Q(n+ 1)=D, D=~Q(n), and clk_out=Q(n+ 1).

Second, odd frequency division: the forum often asks odd frequency division. In fact, there are two ways to realize odd frequency division:

A three-frequency clock with a duty cycle other than 50% can be realized by a counter. For example, for three-frequency division, the rising edge of the clock to be divided triggers the counter to count by three, and when the counter counts to an adjacent value, it flips twice. For example, when the counter counts to 1, the output clock flips, and when the counter counts to 2, the output clock flips again. That is to say, in the adjacent 1 and 2, the count value has been flipped twice. The three-frequency duty ratio achieved in this way is 1/3 or 2/3.

Module 3 (clk_in, rst, clk _ out); ?

Input clk_in, rst

Output clk _ out

Reggie? clk _ out

reg[ 1:0]count； ?

Always @ (negedgrst or posedgclk _ in)

begin

If (rst==0)

begin

Count < = 0;

clk _ out & lt=0;

end

other

Start?

Count & lt = count+1; ?

if(count== 1)

clk _ out & lt= ~ clk _ out

else if(count==2)

begin

clk _ out = ~ clk _ out

Count < = 0;

End?

End?

end

Terminal module

Another implementation:

Module div3(CLKIN, CLKOUT, resetn); ?

Enter CLKIN RESETn?

Output CLKOUT?

Wire d; ?

Reggie? q 1，Q2； ?

Wires? CLKOUT？

Always @(negedge RESETn or posedge CLKIN)?

Start?

if (RESETn== 1'b0)？

q 1 & lt； = 1 ' B0； ?

Or what?

q 1 & lt； = d； //q 1 is the signal that D is delayed by one clock.

end

Always @(negedge RESETn or posedge CLKIN)?

Start?

if (RESETn== 1'b0)？

q2 & lt= 1 ' B0； ?

other

q2 & lt= q 1； //q2 is q 1 signal delayed by one clock.

end

Assignment d = ~ q1&; ~ q2？ //d In one cycle, one clk is high and the other two CLKS are low.

Assignment CLKOUT = q2

Terminal module

In the circuit, it can be realized by two D flip-flops and a simple gate circuit.

If a tri-band clock with a duty ratio of 50% is to be realized, it can be counted by the falling edge of the clock to be divided, and counted by the rising edge, and then the tri-band clock generated by the falling edge and the clock generated by the rising edge are divided by OR, and a tri-band clock with a duty ratio of 50% can be obtained.

This method can realize arbitrary odd frequency division. The general method is as follows: for n odd frequency division with duty ratio of 50%, first trigger the rising edge to count modulo n, then flip the output clock when the count is selected to a certain value, and then flip it by (N- 1)/2 to get the odd frequency division clock with duty ratio of not 50%. Counting the modulus n triggered by the falling edge at the same time, when the value is the same as the selected value of the output clock triggered by the rising edge, flipping the output clock, and when (N- 1)/2 passes, the output clock will flip again to generate an odd-numbered n-divided clock with a duty ratio of not 50%. Two N-divided clocks with a duty ratio of not 50% are AND-operated to obtain odd N-divided clocks with a duty ratio of 50%.

Example: Tri-frequency circuit written in Verilog language.

Method 1:

//Frequency division design triggered by rising edge

Module 3 (clkin, CLKOUT);

Enter clkin// to define the input port.

Output clkout// defines the output?

reg [ 1:0] step 1，step？

Always @ (pose clkin)

begin

Case (step)// This state machine is a counter.

2 ' b00:step & lt； = 2 ' b 0 1；

2 ' b 0 1:step & lt； = 2 ' b 10；

2 ' b 10:step & lt； = 2 ' b00

Default value: step & lt= 2' b00

Close the case

end

Always @(negedgeclkin)? //step 1 differs from step by half clk.

begin

Case (step 1)

2 ' b00:step 1 & lt； = 2 ' b 0 1；

2 ' b 0 1:step 1 & lt； = 2 ' b 10；

2 ' b 10:step 1 & lt； = 2 ' b00

Default value: step1<; = 2 ' b00

Close the case

end

The assignment clkout = step [1] | step1[1]; ? //Flip at 1.5 clk by using the OR operation of step and step 1.

Terminal module

Write a five-frequency circuit with Verilog language, with a duty cycle of 50%;

Module div_5 (clkin, rst, clkout);

Enter clkin, rst

Output clkout

reg [2:0] step 1，step2

Always @ (pose clkin)

If (! rst)

step 1 & lt； = 3 ' b000

other

begin

Case (step 1)

3 ' b000:step 1 & lt； = 3 ' b 00 1；

3 ' b 00 1:step 1 & lt； = 3 ' b 0 1 1；

3 ' b 0 1 1:step 1 & lt； = 3 ' b 100；

3 ' b 100:step 1 & lt； = 3 ' b 0 10；

3 ' b 0 10:step 1 & lt； = 3 ' b000

Default value: step1<; = 3 ' b000

Close the case

end

Always @(negedge clkin)

If (! rst)

Step 2<= 3' b000

other

Starting situation (step 2)

3'b000: step < = 3' b001;

3'b00 1: step < = 3' B011; ? //Note that the order is reversed, so that the cases of the lowest bit 1 are adjacent to each other.

3 ' b 0 1 1:step 2 & lt； = 3 ' b 100；

3'b 100: step < = 3' b 010;

3'b0 10: step < = 3' b000

Default: step & lt= 3' b000

Close the case

end

The assignment clkout = step1[0] | step2 [0]; ? //step 1 and the lowest phase of step2 or

Terminal module

The code of any integer divider is given below:

Module divn(clk, rst_n, o _ clk);

Input clk, rst _ n；;

Output o _ clk

Parameter width = 3;

Parameter N = 5；;

reg [WIDTH- 1:0] cnt_p，CNT _ n； //Count _ Posture, Count _ Negative

Registers clk_p, clk _ n；;

Assignment o_clk = (N== 1)? clk : (N[0])？ (clk _ p & ampclk _ n):clk _ p；

//If N= 1, o _ clk = clk If n is even, o _ clk = clk _ p；; If n is odd, o _ clk = clk _ p &；; clk_n

//is an AND operation, because the high level of clk_p and clk_n is one more clk than the low level, and the difference between them is half a clk. Due to AND, the duty cycle of //o_clk is 50%.

Always @ (posedgclk or negedgrst _ n)

begin

If (! rst_n)

cnt _ p & lt=0;

else if (cnt_p==(N- 1))

cnt _ p & lt=0;

else cnt _ p & lt= CNT _ p+ 1；

end

Always @ (posedgclk or negedgrst _ n)

begin

If (! rst_n)

clk _ p & lt=0;

else if(CNT _ p & lt； (N & gt& gt 1))? //N & gt； & gt 1, when the count reaches N/2, the clock turns over. If CNT _ p

clk _ p & lt=0;

else clk _ p & lt= 1;

end

Always @ (negedgclk or negedgrst _ n)

begin

If (! rst_n)

cnt _ n & lt=0;

else if (cnt_n==(N- 1))

cnt _ n & lt=0;

else cnt _ n & lt= CNT _ n+ 1；

end

Always @ (negedgclk or negedgrst _ n)

begin

If (! rst_n)

clk _ n & lt=0;

else if(CNT _ n & lt； (N & gt& gt 1))

clk _ n & lt=0;

else clk _ n & lt= 1;

End?

Terminal module

Another method: divide the odd clock by n, first by n/2 (with decimal, that is, equal to (n- 1)/2+0.5), and then by 2. Odd frequency doubling with 50% duty cycle is obtained.

Let's talk about the design method of fractional frequency division.

Fractional frequency division: Let's talk about how to divide the frequency by n+0.5, which requires operating the input clock. Basic design idea: divide the frequency by n+0.5, first count the modulus n, when the count reaches n- 1, the output clock is assigned to' 1', and when it returns to count 0, it is assigned to 0. So we can know that when the count value is n- 1, the output clock is only 65438+. It can be found that because the counter is counted by the rising edge of the clock, the counting trigger clock can flip when the count is n- 1, so the falling edge of the clock becomes the rising edge. That is, the falling edge of the clock becomes the rising edge during the counting value of n- 1, so the counting value of n- 1 only lasts for half a clock period, and the counting value becomes 0 because the falling edge of the clock becomes the rising edge. Therefore, the trigger clock should flip once every cycle of the n+0.5 frequency division clock.

Method 2:

//If the duty ratio =50%, the first cycle can be used.

The second cycle outputs the original clock and the third cycle outputs the low level.

This can achieve a frequency division of three,

When the output is divided by three, the duty cycle is 1: 1.

Module 3 (clk, throut)；);

Input clk

Output throughput;

Registers q 1, q2, d, throut

Always @ (pose clk)

If (! d)

q 1 = 1 ' b 1；

other

q 1 = ~ q 1； ?

Always @ (negedgclk)

If (! d)

Q2 = 1 ' b 1；

other

q2 = ~ q2？

Always @(q 1 or q2)

d=q 1。 Q2； //d In one cycle, 0.5 CLKS are high and 1 CLKS are low.

Always @ (posed)

throut = ~ throut

Terminal module

Design of Fractional Frequency Division Arbitrary Integer

Basic principles:

Firstly, two integer frequency dividers with different frequency division ratios are designed by using pulse throughput counter and PLL technology.

Then the required fractional frequency division value can be obtained by controlling the different times of the two frequency division ratios in unit time.

If we design a frequency divider with a frequency division coefficient of 10. 1, we can design the frequency divider to be 9 times of 10 and 1 times of 1, so the total frequency division value is:

f =(9 * 10+ 1 * 1 1)/(9+ 1)= 10. 1

From the characteristics of this implementation, it can be seen that the frequency division value of the frequency divider is constantly changing, and the signal jitter after frequency division is generally large, so it is rarely used in design.

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How to control the pull-up and pull-down of a signal line when writing Verilog code?

For example, when the data arrives, we are pulled down and then pulled up after the data retention time, and there are burrs between the data. At this time, we are already at a low level. That is, after the data arrives for a period of time, WE is pulled down, and when the data is about to change, it is pulled up again, and WE is in the high position of data connection. At first, I felt that the waveform of the clock was quite similar, but it was not well controlled. Sometimes our changes show up in one person. ...

Running eagle owl? |? Browse 506 times

I have a better answer.

Published on 2011-06-1409: 21.

If (data input)

We < = 0;

If (! We)

We<= ~ us;

//This is to lower a clock. If multiple clocks are pulled low, it can be controlled by a counter. The key codes are as follows:

If (data input & cnt = = 5' h13)

We < = 0;

Otherwise start.

We<= 1;

cnt & lt= CNT+ 1；

end

//20 clock cycles lower.

Ask close questions

Here, data_in is a bit of data. If it is multi-bit, such as 4-bit input or more, how to judge the change of data?

One answer after another.

Assuming that the input is a 4-digit number, it can be judged as follows:

for(I = 0； I < = 3; i=i+ 1)

if(data_in[i])？ //or if (! Data_in[i]), which can be selected as required.

.........