The distance from the via to the line is 5mil.

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The rules of line width and line spacing used in Allegro's four-story board are original.

202 1- 1 1-28 00: 14:48

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First, the physical rules:

1. The default wiring uses 4 mil line width;

2. The whole page uses VIA 16D8;

3. Power wiring line width 15mil, neck die 10mil, and the maximum length is 200mil；;

4. The differential pair wiring adopts a line width of 4.5 mils, and generally adopts a line spacing of 5.5 mils;

Note: this four-layer board has no requirement for impedance, so there is no 3W principle for differential pair wiring, and there is no impedance calculation for differential lines;

Second, the spacing rules:

2. 1 line spacing rule

Generally need to set:

Line to line, line to via pin, line to device pin, line to via, line to copper, line to via.

Except that the distance from the line to the hole needs to be set to 6mil, everything else needs to be set to 4 mil.

2.2 Pin spacing rules

It is necessary to set two rows of through-hole pins and surface pins:

Pin to wire, pin to through pin, pin to SMD pin, pin to through hole, pin to shape, pin to hole;

Set the pin-hole ratio to 4 mils except that it is 6 mils;

2.3 via spacing rules

The via spacing rule also needs to set the above six items;

Via to line, via to through pin, via to SMD pin, via to through via, via to shape, via to hole;

It is generally set to 4 mils, and it needs to be set to 6 mils from hole to hole;

2.4 shape spacing rules:

Shape spacing rules also need to set the above six items:

Shape to line, shape to through pin, shape to SMD pin, shape to through via,

Shape to shape, shape to hole;

Generally set to 4 mils, but Shape to shape needs to be set to 10 mils;

The shape of the hole needs to be set to 6 mils;

2.5 hole spacing rules:

The hole spacing is usually set to 6 mils;

Third, the electrical rules:

In this four-layer board, the electrical rules created are mainly differential pairs and equal lengths;

Differential pair: Because the differential pair has been set in the physical rules, the differential pair of this four-layer board can be set to 5mil.

Differential pairs generally compare the lengths of two differential lines, so the requirements are relatively high, and the error is controlled within 5mil. Differential lines are usually wired together.

Equal length: in the setting of physical rules, it can be seen from the schematic diagram that TF card does not need differential wiring, but data and CLK need equal length wiring, so in physical rules, TF card wiring adopts the default, but in electrical wiring, data and CLK wiring must be equal length;

Equal-length wiring, after wiring is completed, the wires that need equal length should be wound according to the rules. You can analyze them by right-clicking in electrical rules, generally taking the longest wire as the baseline, and then winding other wires.

In the interview, when asked about the reference line of DDR length,

Theoretical answer: the data line is based on DQS0 and the address line is based on CLK.

However, the longest trace in the actual project is not necessarily the theoretical baseline, so in the actual project, Analyze often takes the longest trace as the baseline, and the length of other traces approaches the length of the longest line to meet the DRC requirements.

Reason: the longest line is difficult to shorten, and the short line can be wound long.

The long one can't be short, and the short one can be wound.

Differential pair screenshot:

Equal length screenshot:

Open CSDN for a better reading experience.

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